Define architecture of NVMe 1.3 design. RTL design. Microarchitecture analysis and supervision of a team of design and verification engineers.


  • Recognized expert in NVMe for consumer through hyperscale applications.
  • Hands on knowledge of PCIe and AMBA.
  • Prior experience in bringing up NVMe systems. Familiarity of firmware requirements.
  • SOC/ASIC/IP development with proficiency in front-end tools (including logic simulator, lint, CDC, synthesis, Logic Equivalence Checker, formal and static timing analysis) and methodologies.
  • Proficient in Verilog and System Verilog.
  • Knowledge of design verification and scripting language such as perl/tcl is desirable.


  • The candidate will be responsible for driving our NVMe 1.3 design across an array of SOC applications. Perform architecture analysis and define functional specification with input from firmware architects and networking designers. Design in Verilog or high-level synthesis. Support verification, circuit, and test groups throughout design cycle and silicon bring up. Work with multi-disciplinary groups to ensure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design flow. International travels may be required.


  • Master’s degree in Computer Science or Electrical Engineering with at least 10-year work experience.
  • Ph.D degree in Computer Science or Electrical Engineering with a qualified professional background.

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