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XITC5088 Accelerator


Product Overview

The XITC5088 Accelerator provides high performance enterprise level data protection, data compression, data decompression, data recovery functions. This product can provide the perfect support for consumer and enterprise level computing and storage applications. The XITC5088 accelerator is designed to combine high performance with robustness and ease of use and integration. The XITC5088 is designed to allow up to six different simultaneous data operations.

This accelerator IP is designed as a block-IO device to be attached to the host either directly through a PCIe bus, or supporting multiple Hosts through a PCIe switch. The host can move data blocks to the XITC5088 accelerator SOC for data encryption, data decryption, data compression, data decompression, as well as erasure coding parity generation, erasure coding data validation and erasure coding data recovery. This SOC will also include various security functions such as Key generation (both symmetric and asymmetric), digital signing, verification, hash generation and MAC functions. XITC5088 also employs a feature to allow the Host to perform two data operations using a single data transfer, with inputting only a single command.

The ECS Coding and Data Retrieval operation is a high-performance feature specific to XITC5088. This function allows for high speed data recovery of multiple data segments/drives by using a reduced number of “Parity” Drives specified by the Host. This ECS operation uses polynomials, Galois Field (GF) values, as well as exponential, logarithmic and matrix math functions to provide a very efficient storage method, allowing for recovering data from multiple, simultaneous drive failures.


High Performance
◇ Industrial standard PCIe Revision 3.1 compliant
◇ Multi-port PCIE x8, x4, x2 and x1 lane mode, including supporting bifurcation into 2 port X 4 lane configurations
◇ PCIe low power management, ASPM L0s, L1, L1.2, PCI PM D0-D3 state
◇ NVMe Revision 1.3 with NVMe Vendor Specific Commands
◇ NVMe CMB Functionality
◇ Supports both NVMe PRP and SGL formats
◇ Supports up to 66 admin and 128 IO Queue pairs
◇ Supports up to 128 Namespaces
◇ Supports up to two Physical Functions, one Physical Function per PCIe Port
◇ SR-IOV support with a maximum of 128 total Virtual Functions
Data Protection and Reliability
◇ Data protected with overlapping ECC and CRC/Parity protection mechanisms
◇ Single bit of correction and 2 bits of detection (SECDED) used for all data stored within SOC
Enhanced Security
◇ High Performance Security Processing for
— RSA1024, RSA2048, RSA 3072, RSA4096
— AES128, AES 256
— SM2
— SM4
— Diffie-Hellman
◇ 64KB SPI ROM for encryption key storage of up to 128 different keys
◇ Support SHA-1, SHA224,SHA256, SHA384, SHA512 and SM3 Hashing
◇ Support for CMAC, CBC, and GCM cipher modes
◇ Hardware True Random Number Generator (TRNG)
◇ OTP for security and H/W control/protection
Erasure Correction Sequence (ECS)
◇ Configurable Erasure Correction size
◇ Erasure Parity Coding to allow for data recovery
◇ Erasure Correction Coding for actual data recovery
◇ Erasure Coding Checking for data validation


Goke US Research Laboratory
4655 Old Ironsides Dr, #350
Santa Clara, CA 95054


Main: +1.408.868.7988
Fax: +1.408.849.4913

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