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ENGINEER - SR. STAFF DESIGN

Be involved in developing storage chipsets, and be responsible for driving our NVMe design across an array of SOC applications.

JOB DUTIES:

  • Be responsible for defining functional specification with the ASIC architect and developing the design in Verilog.
  • Be responsible for micro architecture design in Verilog (e.g. FSM, Data-Path/Control-Path Designs, etc.) that produces reasonable post-synthesis designs in terms of timing and area.
  • Perform functional verification, circuit, and test groups throughout design cycle and silicon bring up.
  • Develop SOC/IP with leading-edge automation tools and methodologies, including logic simulator, SpyGlass, Design Compiler, and static timing analysis.
  • Be responsible for implementing ARM architecture and interface technology such as AXI, PCIe, and NVMe.
  • Conduct Error Correcting Code (ECC) Logic Design.
  • Build test bench and test cases using C.
  • Perform design synthesis, timing closure, design for test, and form verification using scripting language such as Perl or TCL.

JOB REQUIREMENTS:

  • Master’s degree in Electrical Engineering/Electronics Engineering, plus 6 months experience in the job offered or as an ASIC Design Engineer.
  • Must be proficient in using: VCS, PrimeTime, Design Compiler, SpyGlass, Tessent, LEC.

JOB AND INTERVIEW:

  • Santa Clara, CA. 40 hours/week
Mobirise
Offices

Goke US Research Laboratory
4655 Old Ironsides Dr, #350
Santa Clara, CA 95054

Contact

Email: info@gokeuslab.com
Main: +1.408.868.7988
Fax: +1.408.849.4913

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