In this highly visible role, the candidate will become one of the major contributors to next-generation chipsets for data storage using state-of-the-art technologies. You are expected to participate in defining functional specification and micro-architecture of IP/Chip-level development.
Hands-on SOC/ASIC/IP development with proficiency in front-end tools (including logic simulator, lint, CDC, SpyGlass, Design Compiler, Logic Equivalence Checker, formal and static timing analysis) and methodologies.
RTL coding capability with Verilog (e.g. FSM, Data-Path/Control-Path Designs, etc..) that produces reasonable post-synthesis designs in terms of timing and area.
Behavioral coding with System Verilog/Verilog.
Knowledge of NAND flash devices and SSD is a plus.
Hands on Experience in Error Correcting Code (ECC) Logic Design (LDPC preferred) or DSP Logic Design is a plus.
Knowledge of design verification and a scripting language such as PERL/TCL is desirable.
Knowledge of C or C+.
Strong problem solving, debugging, analytical skills.
The candidate will be involved in developing storage chipsets. The work requires participation in defining ECC specification with the ASIC architect and developing the ECC design in Verilog. Support verification, circuit, and test groups throughout the design cycle and silicon bring up. Work with multi-disciplinary groups to ensure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design flow. Occasional international travels may be required.
Master degree with at least 3-year work experience.
Ph.D. degree with a qualified professional background.
Goke US Research Laboratory 4655 Old Ironsides Dr, #350
Santa Clara, CA 95054