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ENGINEER - VERIFICATION

JOB DESCRIPTION:

  • Development of the verification infrastructure in UVM/System Verilog for block-level/chip-level design verification.
  • Create and maintain detailed test plans to ensure the quality and performance are met. Define and implement functional coverage, and enhance the test bench to ensure coverage closure.
  • Design the architecture of the IC chip. Write the verification plans, determine the parameters and write test benches, verify the test for the IC chip designs.
  • Develop dashboard and coverage and debug the code coverage for the next generation chip design.
  • Work with Design Engineers to debug functional errors in RTL/RTL models.
  • Participate in design reviews and recommend improvements. Collaborate with Design Engineering team to debug functional errors in RTL/RTL models.

REQUIREMENTS:

  • Job entails working with and requires Master’s degree in Electrical Engineering, or equivalent with 2 years of experience including: Verilog, System Verilog, Python, UVM, ASIC Design Verification Flow, CPU Architecture, C++,Linux. Relevant industrial experience preferred.
  • Employer will accept any suitable combination of education, training or experience. This should be read to mean that the employer requires: Master’s degree in Electrical Engineering, or Equivalent with 2 years of experience in the job offered, Verification Engineer, Design Verification Engineer, or Equivalent.
  • To apply, please mention Job Code VM01 and mail resume to: Goke US Research Laboratory, HR, 4655 Old Ironsides Dr, #350, Santa Clara, CA 95054
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Offices

Goke US Research Laboratory
4655 Old Ironsides Dr, #350
Santa Clara, CA 95054

Contact

Email: info@gokeuslab.com
Main: +1.408.868.7988
Fax: +1.408.849.4913

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