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In this highly visible role, the candidate will become one of the major contributors to next generation chipsets for data storage using state-of-the-art technologies. You are expected to utilize cutting-edge methodologies to perform block-level/chip-level design verification with given performance requirements.


  • BSEE or MSEE, with experience in supporting both IP & SOC verification environment.
  • 3+ years of experience using advanced verification methodologies, such as UVM System Verilog, constrained-random stimulus generation, assertion-based verification, and functional -coverage techniques.
  • Understanding of AMBA, PCIe, SATA/SAS, NVMe is required.
  • Knowledge of C or C+.
  • Strong problem solving, debugging, analytical skills.


  • Experience in ARM based SOC verification.
  • Understanding of AMBA, PCIe, SATA/SAS, NVMe is required.
  • Experience with Python, Perl, Tcl, C/C++ and shell scripts is a desirable.
  • Knowledge of NAND flash devices and SSD is a plus.


You will be responsible for ensuring the quality of the IP/SOC & are expected to:

  • Develop IP/subsystem/SOC test bench, create tests, and necessary coverage goals based on specification to verify the implementation.
  • Participate in defining functional specification with the architect and develop the design in Verilog with verification engineers.
  • Support gate level functional verification, run regressions, manage bug tracking, analyze code & functional coverage.
  • Apply advanced techniques to achieve verification and validation with the highest quality, productivity.
  • Support verification, circuit, and test groups throughout design cycle and silicon bring up.
  • Work with multi-disciplinary groups to ensure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design flow.
  • Work independently & manage deliverables to align with the project goal.
  • Develop, and maintain UVM based co-simulation environment, that include checkers, BFMs, monitors, DPI interface to reference model.
  • Occasional international travels may be required.


  • Bachelor's degree (B. A.) with at least 5-year work experience.
  • Master’s degree with at least 3-year work experience.
  • Ph.D degree with a qualified professional background.

Goke US Research Laboratory
4655 Old Ironsides Dr, #350
Santa Clara, CA 95054


Main: +1.408.868.7988
Fax: +1.408.849.4913

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