Job08

ENGINEER - SR./VERIFICATION

BSEE or MSEE, with experience in supporting both IP & SOC verification environment.
3+ years of experience using advanced verification methodologies, such as UVM System Verilog, constrained-random stimulus generation, assertion-based verification, and functional -coverage techniques.
Understanding of AMBA, PCIe, SATA/SAS, NVMe is required.
Knowledge of C or C+.
Strong problem solving, debugging, analytical skills.

Develop IP/subsystem/SOC test bench, create tests, and necessary coverage goals based on specification to verify the implementation.
Participate in defining functional specification with the architect and develop the design in Verilog with verification engineers.
Support gate level functional verification, run regressions, manage bug tracking, analyze code & functional coverage.
Apply advanced techniques to achieve verification and validation with the highest quality, productivity.
Support verification, circuit, and test groups throughout design cycle and silicon bring up.
Work with multi-disciplinary groups to ensure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design flow.
Work independently & manage deliverables to align with the project goal.
Develop, and maintain UVM based co-simulation environment, that include checkers, BFMs, monitors, DPI interface to reference model.
Occasional international travels may be required.